1. Field of the Invention
The present invention relates to package structures, and, more particularly, to a package structure for preventing electromagnetic interferences, and a method of manufacturing the package structure.
2. Description of Related Art
With the advancement in the technology of semiconductor package, different package structures have been developed to be incorporated in the smart phones, tablets, internet, laptops, and such semiconductor device is formed by mounting a chip on a package substrate such that the semiconductor chip is electrically connected thereto, and then followed by an encapsulating process to complete the formation of the semiconductor device. In addition, a package with an embedded chip which has the chip embedded in a package substrate is developed so as to reduce the overall thickness of the semiconductor package. Such semiconductor package is gaining popularity as it has the advantages of reduced size as well as improved electronic performance.
FIGS. 1A to 1D are cross-sectional views showing a conventional package structure 1. As shown in FIG. 1A, a core board 13 having an opening 130 penetrating therethrough is prepared. A plurality of inner wirings 11 and a copper window 110 are formed on upper and lower sides of the core board 13. A plurality of conductive pillars 12 are formed in the core board 13 are electrically connected with the inner wirings 11.
As shown in FIG. 1B, a carrier board 10 is disposed on a bottom side of the core board 13. Polyimide (PI) adhesive tapes secure a semiconductor chip 18 having a plurality of electrode pads 180 to be accommodated in the opening 130. The semiconductor chip 18 is disposed on the carrier board 10. Through the design of the copper window 110, the semiconductor chip 18 can be prevented from making contact with the inner wirings 11.
As shown in FIG. 1C, a dielectric layer is laminated on an upper side of the core board 13 and on the semiconductor chip 18. A dielectric material fills a gap between a wall of the opening 130 and the semiconductor chip 18. The carrier board 10 is then removed. Another dielectric material is laminated on the bottom side of the core board 13. The two dielectric materials form a dielectric material layer 16.
As shown in FIG. 1D, two wiring layers 14 are formed on the upper and lower sides of the dielectric material layer 16, respectively. The wiring layer 14 has conductors 15 disposed in the dielectric material layer 16 and electrically connected with the electrode pads 180 and the inner wirings 11.
However, in the manufacturing process of the conventional package structure 1, since the copper window 110 is used as a blocking layer, the inner wirings 11 have a layout area that is reduced. Besides, as the opening 130 is formed by a CO2 laser process, the package structure 1 has a high cost, and organic fiberglass of the core board 13 is likely exposed therefrom. Therefore, the package structure 1 has a low yield rate and poor quality.
Blind holes (that are formed where the conductors 15 are disposed) or vias (that are formed where the conductive pillars 12 are disposed) are required to be formed by a laser process. The blind holes and vias thus formed can be circular only, and have poor quality.
PI tapes are used to secure the semiconductor chip 18 to the carrier board 10. The attachment and detachment of the PI tapes to and from the carrier board 10 adversely increase the overall cost of the package structure 1.
Furthermore, two dielectric materials are required to be laminated to form the dielectric material layer 16. The additional lamination and cure process increase the overall cost and time required to manufacture the package structure 1, and may lead to displacement of the semiconductor chip 18 (or even rotation). Therefore, it is difficult to precisely position the semiconductor chip 18 in the opening 130, and the electrode pads 180 of the semiconductor chip 18 are inaccurately aligned with the conductors 15. As a result, the electrical connection is poor, and the package structure 1 thus has a low yield rate.
FIGS. 1A′ to 1D′ are cross-sectional views showing a method of manufacturing another conventional package structure 1′.
As shown in FIG. 1A′, a first wiring layer 11′ is formed on the carrier board 10 such as a copper coil substrate, and a passive component 18′ such as a multi-layer ceramic capacitor (MLCC) is secured on the first wiring layer 11′ via an insulating adhesive material 180. As shown in FIG. 1B′, a first dielectric material layer 13′ having a penetrating opening 130 is formed on the carrier board 10, and a passive component 18′ is received in the opening 130.
As shown in FIG. 1C′, a second dielectric material layer is laminated on the upper side of the first dielectric material layer 13′ and on the passive component 18′, and fills a gap between a wall of the opening 130 and the passive component 18′. The first dielectric material layer 13′ and the second dielectric layer to form a dielectric encapsulating layer 16′ that encapsulates and secures the passive component 18′ and the first wiring layer 11′.
As shown in FIG. 1D′, a second wiring layer 14′ is formed on the upper side of the dielectric encapsulating layer 16′. The second wiring layer 14′ has conductors 15 disposed in the dielectric encapsulating layer 16′ and electrically connected with the passive component 18′. Subsequently, the carrier board 10 is removed to expose the first wiring layer 11′.
In the conventional package structure 1′, since the copper coil substrate is used as the carrier board 10, it is easy to cause delamination, and the package structure 1′ is damaged. A laser process is required to form blind holes (that are formed where the conductors 15 are disposed). However, the laser process can form circular blind holes only, and the blind holes have poor quality.
Furthermore, since attaching the passive component 18′ is achieved through non-conductive material and a dispensing method, the diameter of dispensing adhesive is larger than 200 μm and is difficult to control the volume of each dispensing adhesive, it is very easy for the insulating adhesive material 180′ to spread to other areas, causing the wirings between each of the first wiring layer 11′ to attach to the adhesive, thereby undesirably lowering the reliability.
After another two processes of making the dielectric material layer, the dielectric encapsulating layer 16′ is formed by a lamination process, however as the first dielectric material layer 13 and the second dielectric material layer can be mistakenly placed, not only this increases the time and cost, because the passive component 18′ has not yet been secured in place before baking the passive component 18′, but also the passive component 18′ may easily become displaced, causing a loss in yield.
In addition, using conductors 15 as a means to electrically connect the passive component 18′ may increase the electrical pathway and signal loss, and the cost of using copper electrodes (MLCC) as the passive component 18′ is also very high.
Therefore, there is an urgent need to solve the above-mentioned drawbacks of the conventional technology.